This invention relates to a method of gettering layer that can remove impurities or eliminate imperfections of element so as to improve chemical mechanical polishing process during flash-memory production.
The widely implemented nonvolatile memory may be divided into the categories including: read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory.
The low-price masked ROM is considered more profitable for mass production on the one hand, however, a vital loss beyond compensation might be resulted in the case of errors made in program or data on the other hand.
On the contrary, the high-cost EPROM can be programmed and erased repeatedly usually in some ten times, therefore, it would rather be fit for a small quantity production.
Programming or erasing of the EEPROM and flash memory can be performed by controlling charge or discharge of the gate. Efforts have been continuously made on the nonvolatile memory trying for further shortening the programming and the erasing time, lowering the working voltage and the device measurements, and lengthening the data preservable time.
The floating gate voltage (Vt) of the flash memory will drop down rapidly when it is baked around 250xc2x0 C. because of the electrically combination of electrons and holes in the floating gate. As illustrated in FIG. 1, a conventional intermediate layer dielectric (ILD) of boron phosphor silicate glass (BPSG) is implemented for covering an element and serving as a gettering layer or a trapping layer so as to resist against moisture or catch mobile ions, wherein, for increasing flattening margin, the thickness of the ILD is determined subject to the pattern density so that the Vt may be affected after baking.
In order to improve the degraded reliability of a flash memory after baking, also the dielectrics of an intermediate layer dielectric (ILD) when flattening the margin of the dielectrics with chemical mechanical polishing (CMP), and enlargement of thickness margin of peripheral ILD and dense array, a method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile ion with the gettering layer. Moreover, by taking advantage of the gettering layer, reduction of the thickness of the ILD for increasing the etching margin, the deposition margin, and the remaining margin of oxides are made possible.
For realizing abovesaid objects, the method of gettering layer for improving chemical mechanical polishing process in flash-memory production comprises:
providing a substrate, whereon at least a memory structure layer is disposed;
depositing a first dielectric layer, which is formed lying on the memory structure layer;
depositing a gettering layer, which is formed lying on the first dielectric layer;
forming a second dielectric layer lying on the gettering layer; and
flattening the second dielectric layer with a chemical mechanical polisher.
For more detailed information regarding this invention together with advantages or features thereof, at least an example of preferred embodiment will be elucidated below with reference to the annexed drawings.